forked from github/verilator
147 lines
2.6 KiB
Systemverilog
147 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int a;
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int b;
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int c;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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end
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// NOTE this grammar hasn't been checked with other simulators,
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// is here just to avoid uncovered code lines in the grammar.
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property p_strong;
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strong(a);
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endproperty
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property p_weak;
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weak(a);
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endproperty
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property p_until;
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a until b;
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endproperty
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property p_suntil;
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a s_until b;
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endproperty
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property p_untilwith;
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a until_with b;
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endproperty
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property p_suntilwith;
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a s_until_with b;
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endproperty
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property p_implies;
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a implies b;
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endproperty
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property p_poundminuspound1;
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a #-# b;
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endproperty
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property p_poundeqpound;
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a #=# b;
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endproperty
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property p_nexttime;
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nexttime a;
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endproperty
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property p_nexttime2;
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nexttime [2] a;
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endproperty
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property p_snexttime;
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s_nexttime a;
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endproperty
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property p_snexttime2;
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s_nexttime [2] a;
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endproperty
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property p_nexttime_always;
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nexttime always a;
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endproperty
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property p_nexttime_always2;
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nexttime [2] always a;
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endproperty
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property p_nexttime_eventually;
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nexttime eventually a;
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endproperty
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property p_nexttime_eventually2;
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nexttime [2] always a;
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endproperty
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property p_nexttime_seventually;
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nexttime s_eventually a;
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endproperty
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property p_nexttime_seventually2;
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nexttime s_eventually [2:$] always a;
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endproperty
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property p_accepton;
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accept_on (a) b;
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endproperty
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property p_syncaccepton;
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sync_accept_on (a) b;
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endproperty
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property p_rejecton;
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reject_on (a) b;
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endproperty
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property p_syncrejecton;
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sync_reject_on (a) b;
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endproperty
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property p_iff;
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a iff b;
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endproperty
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property p_arg_propery(property inprop);
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inprop;
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endproperty
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property p_arg_seqence(sequence inseq);
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inseq;
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endproperty
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property p_case_1;
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case (a) endcase
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endproperty
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property p_case_2;
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case (a) default: b; endcase
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endproperty
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property p_if;
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if (a) b
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endproperty
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property p_ifelse;
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if (a) b else c
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endproperty
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always @(posedge clk) begin
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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