forked from github/verilator
10 lines
617 B
Plaintext
10 lines
617 B
Plaintext
%Error: t/t_assert_procedural_clk.v:21:13: Unsupported: Procedural concurent assertion with clocking event inside always (IEEE 1800-2917 16.14.6)
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: ... In instance t
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21 | assume property (@(posedge clk) cyc == 9);
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| ^~~~~~
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%Error: t/t_assert_procedural_clk.v:22:13: Unsupported: Procedural concurent assertion with clocking event inside always (IEEE 1800-2917 16.14.6)
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: ... In instance t
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22 | assume property (@(negedge clk) cyc == 9);
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| ^~~~~~
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%Error: Exiting due to
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