forked from github/verilator
29 lines
807 B
Systemverilog
29 lines
807 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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int cyc = 0;
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logic val = 0;
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// Example:
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always @(posedge clk) begin
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cyc <= cyc + 1;
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val = ~val;
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$display("t=%0t cyc=%0d val=%b", $time, cyc, val);
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0)
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else $display("$past assert 1 failed");
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assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1)
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else $display("$past assert 2 failed");
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// Example end
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endmodule
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