forked from github/verilator
31 lines
626 B
Systemverilog
31 lines
626 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg [1:0] value;
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initial begin
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value = 2'b00;
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unique casez (value)
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2'b00 : ;
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2'b01 : ;
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2'b1? : ;
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endcase
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value = 2'b11;
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unique casez (value)
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2'b00 : ;
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2'b01 : ;
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2'b1? : ;
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endcase
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unique casez (1'b1)
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default: ;
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endcase
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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