forked from github/verilator
41 lines
1.1 KiB
Systemverilog
41 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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//bug991
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module t (/*AUTOARG*/);
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logic [31:0] array_assign [3:0];
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logic [31:0] array_other [3:0];
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logic [31:0] larray_assign [0:3];
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logic [31:0] larray_other [0:3];
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initial begin
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array_assign[0] = 32'd1;
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array_assign[3:1] = '{32'd4, 32'd3, 32'd2};
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array_other[0] = array_assign[0]+10;
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array_other[3:1] = array_assign[3:1];
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if (array_other[0] != 11) $stop;
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if (array_other[1] != 2) $stop;
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if (array_other[2] != 3) $stop;
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if (array_other[3] != 4) $stop;
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larray_assign[0] = 32'd1;
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larray_assign[1:3] = '{32'd4, 32'd3, 32'd2};
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larray_other[0] = larray_assign[0]+10;
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larray_other[1:3] = larray_assign[1:3];
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if (larray_other[0] != 11) $stop;
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if (larray_other[1] != 4) $stop;
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if (larray_other[2] != 3) $stop;
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if (larray_other[3] != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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