forked from github/verilator
96 lines
2.4 KiB
Systemverilog
96 lines
2.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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typedef struct packed {
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logic [7:0] a;
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} tb_t;
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typedef struct packed {
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// verilator lint_off LITENDIAN
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logic [0:7] a;
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// verilator lint_on LITENDIAN
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} tl_t;
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typedef struct packed {
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logic [7:0] bb;
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// verilator lint_off LITENDIAN
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tb_t [0:1] cbl;
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tb_t [1:0] cbb;
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tl_t [0:1] cll;
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tl_t [1:0] clb;
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logic [0:7] dl;
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// verilator lint_on LITENDIAN
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} t2;
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logic [2:0][31:0] test2l;
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// verilator lint_off LITENDIAN
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logic [0:2][31:0] test2b;
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logic [0:2][31:0] test1b;
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// verilator lint_on LITENDIAN
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logic [2:0][31:0] test1l;
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module t;
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t2 t;
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initial begin
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t = 80'hcd_1f2f3f4f_5f6f7f8f_c2;
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`checkh(t.bb, 8'hcd);
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`checkh(t.cbl[0].a, 8'h1f);
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`checkh(t.cbl[1].a, 8'h2f);
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`checkh(t.cbb[0].a, 8'h4f);
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`checkh(t.cbb[1].a, 8'h3f);
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`checkh(t.cll[0].a, 8'h5f);
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`checkh(t.cll[1].a, 8'h6f);
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`checkh(t.clb[0].a, 8'h8f);
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`checkh(t.clb[1].a, 8'h7f);
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`checkh(t.dl, 8'hc2);
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t = '0;
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t.bb = 8'h13;
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t.cbl[0].a = 8'hac;
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t.cbl[1].a = 8'had;
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t.cbb[0].a = 8'hae;
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t.cbb[1].a = 8'haf;
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t.cll[0].a = 8'hbc;
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t.cll[1].a = 8'hbd;
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t.clb[0].a = 8'hbe;
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t.clb[1].a = 8'hbf;
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t.dl = 8'h31;
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`checkh(t, 80'h13_acadafae_bcbdbfbe_31);
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t = '0;
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t.bb[7] = 1'b1;
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t.cbl[1].a[1] = 1'b1;
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t.cbb[1].a[2] = 1'b1;
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t.cll[1].a[3] = 1'b1;
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t.clb[1].a[4] = 1'b1;
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t.dl[7] = 1'b1;
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`checkh(t, 80'h80_0002040000100800_01);
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test1b = '{0, 1, 2};
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test1l = test1b;
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test2l = '{2, 1, 0};
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test2b = test2l;
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`checkh(test2l[0], 0);
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`checkh(test2l[2], 2);
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`checkh(test2l, {32'h2, 32'h1, 32'h0});
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`checkh(test2b[0], 2);
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`checkh(test2b[2], 0);
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`checkh(test2b, {32'h2, 32'h1, 32'h0});
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`checkh(test1b[0], 0);
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`checkh(test1b[2], 2);
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`checkh(test1b, {32'h0, 32'h1, 32'h2});
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`checkh(test1l[0], 2);
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`checkh(test1l[2], 0);
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`checkh(test1l, {32'h0, 32'h1, 32'h2});
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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