forked from github/verilator
132 lines
2.7 KiB
Systemverilog
132 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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string test_string = "abcd";
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int array3d[2][3][4] = '{
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'{
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'{ 0, 1, 2, 3},
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'{ 4, 5, 6, 7},
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'{ 8, 9, 10, 11}
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},
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'{
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'{ 12, 13, 14, 15},
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'{ 16, 17, 18, 19},
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'{ 20, 21, 22, 23}
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}
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};
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int pos;
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int val;
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int i;
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byte b;
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int data[4] = '{1, 2, 3, 4};
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generate
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genvar j;
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int gdata[4];
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for (j=0; j < 5; j++) begin
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initial if (j >= 5) $stop;
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end
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for (j=0; j < 5; ++j) begin
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initial if (j >= 5) $stop;
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end
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for (j=10; j >= 5; j--) begin
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initial if (j < 5) $stop;
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end
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for (j=10; j >= 5; --j) begin
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initial if (j < 5) $stop;
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end
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endgenerate
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initial begin
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pos = 0;
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pos++;
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if (pos != 1) $stop;
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array3d[0][0][0]++;
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if (array3d[0][0][0] != 1) $stop;
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--array3d[0][0][0];
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if (array3d[0][0][0] != 0) $stop;
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pos = 2;
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b = test_string[--pos];
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if (b !== "b") $stop;
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if (pos !== 1) $stop;
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pos = 1;
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b = test_string[++pos];
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if (b !== "c") $stop;
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if (pos !== 2) $stop;
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pos = 3;
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b = test_string[pos--];
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if (b !== "d") $stop;
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if (pos !== 2) $stop;
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pos = 0;
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b = test_string[pos++];
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if (b !== "a") $stop;
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if (pos !== 1) $stop;
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pos = 0;
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val = array3d[++pos][--pos][++pos];
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if (pos !== 1) $stop;
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if (val !== 13) $stop;
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pos = 0;
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val = array3d[++pos][pos--][++pos];
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if (pos !== 1) $stop;
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if (val !== 17) $stop;
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for (i=0; data[++i]<4;) begin
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// loop with multiple statements
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pos = i;
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val = data[i];
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end
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if (pos !== 2) $stop;
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if (i !== 3) $stop;
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if (val !== 3) $stop;
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i = 0;
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while (data[i++]<4) begin
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// loop with multiple statements
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pos = i;
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val = data[i];
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end
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if (pos !== 3) $stop;
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if (i !== 4) $stop;
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if (val !== 4) $stop;
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pos = 0;
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if (1 == 1) begin
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pos++;
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end
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if (pos != 1) $stop;
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pos = 0;
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if (1 == 1) pos++;
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if (pos != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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