forked from github/verilator
153 lines
4.5 KiB
Systemverilog
153 lines
4.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [15:0] m_din;
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// OK
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reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5;
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always @ (posedge clk) begin
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if (cyc==0) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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c_split_1 <= 16'h0;
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c_split_2 <= 16'h0;
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c_split_3 <= 16'h0;
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c_split_4 <= 0;
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c_split_5 <= 0;
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// End of automatics
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end
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else begin
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c_split_1 <= m_din;
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c_split_2 <= c_split_1;
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c_split_3 <= c_split_2 & {16{(cyc!=0)}};
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if (cyc==1) begin
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c_split_4 <= 16'h4;
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c_split_5 <= 16'h5;
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end
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else begin
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c_split_4 <= c_split_3;
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c_split_5 <= c_split_4;
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end
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end
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end
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// OK
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reg [15:0] d_split_1, d_split_2;
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always @ (posedge clk) begin
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if (cyc==0) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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d_split_1 <= 16'h0;
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d_split_2 <= 16'h0;
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// End of automatics
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end
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else begin
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d_split_1 <= m_din;
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d_split_2 <= d_split_1;
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d_split_1 <= ~m_din;
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end
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end
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// Not OK
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always @ (posedge clk) begin
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if (cyc==0) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// End of automatics
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end
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else begin
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$write(" foo %x", m_din);
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$write(" bar %x\n", m_din);
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end
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end
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// Not OK
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reg [15:0] e_split_1, e_split_2;
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always @ (posedge clk) begin
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if (cyc==0) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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e_split_1 = 16'h0;
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e_split_2 = 16'h0;
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// End of automatics
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end
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else begin
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e_split_1 = m_din;
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e_split_2 = e_split_1;
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end
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end
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// Not OK
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reg [15:0] f_split_1, f_split_2;
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always @ (posedge clk) begin
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if (cyc==0) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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f_split_1 = 16'h0;
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f_split_2 = 16'h0;
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// End of automatics
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end
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else begin
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f_split_2 = f_split_1;
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f_split_1 = m_din;
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end
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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//$write(" C %d %x %x\n", cyc, c_split_1, c_split_2);
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cyc<=cyc+1;
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if (cyc==1) begin
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m_din <= 16'hfeed;
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end
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if (cyc==3) begin
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end
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if (cyc==4) begin
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m_din <= 16'he11e;
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if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
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if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
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if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
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end
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if (cyc==5) begin
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m_din <= 16'he22e;
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if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
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// Two valid orderings, as we don't know which posedge clk gets evaled first
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if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
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if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
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end
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if (cyc==6) begin
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m_din <= 16'he33e;
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if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop;
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if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
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// Two valid orderings, as we don't know which posedge clk gets evaled first
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if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
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if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
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end
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if (cyc==7) begin
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m_din <= 16'he44e;
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if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop;
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end
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if (cyc==8) begin
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m_din <= 16'he55e;
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if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e
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&& c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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