forked from github/verilator
59 lines
1.4 KiB
Systemverilog
59 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Values to swap and locations for the swapped values.
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wire [31:0] x_fwd = 32'hdeadbeef;
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wire [31:0] y_fwd;
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wire [31:0] x_bwd;
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wire [31:0] y_bwd = 32'hfeedface;
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swap swap_fwd_i (.a (x_fwd),
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.b (y_fwd));
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swap swap_bwd_i (.a (x_bwd),
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.b (y_bwd));
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write ("x_fwd = %x, y_fwd = %x\n", x_fwd, y_fwd);
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$write ("x_bwd = %x, y_bwd = %x\n", x_bwd, y_bwd);
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`endif
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if (y_fwd != 32'hefbeadde) $stop;
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if (x_bwd == 32'hcefaedfe) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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// Swap the byte order of two args.
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module swap (
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inout wire [31:0] a,
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inout wire [31:0] b
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);
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alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b;
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// Equivalent to
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// wire [31:0] a_prime;
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// wire [31:0] b_prime;
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// assign b_prime = {a[7:0],a[15:8],a[23:16],a[31:24]};
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// assign {a_prime[7:0],a_prime[15:8],a_prime[23:16],a_prime[31:24]} = b;
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// assign b = b_prime;
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// assign a = a_prime;
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endmodule
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