forked from github/verilator
42 lines
897 B
Systemverilog
42 lines
897 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Values to swap and locations for the swapped values.
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reg [31:0] x = 32'ha5a5a5a5;
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wire [31:0] y;
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testit testi_i (.a (x[7:0]),
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.b (y[31:24]));
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always @ (posedge clk) begin
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x <= {x[30:0],1'b0};
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$write("x = %x, y = %x\n", x, y);
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if (x[3:0] != 4'h0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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// Swap the byte order of two args.
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module testit (input wire [7:0] a,
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output wire [7:0] b
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);
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alias b = {a[3:0],a[7:4]};
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endmodule
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