forked from github/verilator
44 lines
681 B
Systemverilog
44 lines
681 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ns
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module t;
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p p ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`timescale 1ns/1ns
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program p;
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endprogram
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`celldefine
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`timescale 1ns/1ns
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primitive a_udp(out, in);
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output out;
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input in;
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reg out;
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table
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0 : 1;
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1 : 0;
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? : ?;
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x : x;
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endtable
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endprimitive
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`endcelldefine
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`celldefine
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module c_not(in, out);
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input in;
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output out;
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assign out = !in1;
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endmodule
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`endcelldefine
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