forked from github/verilator
58 lines
1.1 KiB
Systemverilog
58 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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q0, q1, q2, q3, q4,
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// Inputs
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clk, rst, en, i0, i1, i2, i3, i4
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);
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input clk;
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input rst;
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input en;
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output int q0; input int i0;
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output int q1; input int i1;
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output int q2; input int i2;
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output int q3; input int i3;
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output int q4; input int i4;
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always @ (posedge clk) begin
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if (rst) begin
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if (en) q0 <= i0;
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end
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else q0 <= 0;
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if (rst) begin
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if (en) q1 <= i1;
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end
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else q1 <= 0;
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if (rst) begin
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if (en) q2 <= i2;
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end
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else q2 <= 0;
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if (rst) begin
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if (en) q3 <= i3;
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end
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else q3 <= 0;
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end
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always_comb begin
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q4 = i4;
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if (q4 == 0) begin
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// Conflicts with condition
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q4 = 1;
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end
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if (q4 == 0) begin
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// Conflicts with condition
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q4 = 2;
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end
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end
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endmodule
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