forked from github/verilator
77 lines
1.5 KiB
Systemverilog
77 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Peter Monsson.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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wire gain = 1'b0;
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real in;
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always_comb in = (cyc-4) * 1.0;
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wire cmp;
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adc_netlist netlist(.clk, .in, .gain, .cmp);
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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$display("cyc=%0d cmp=%d", cyc, cmp);
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if (cyc == 3) begin
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if (cmp != 0) $stop;
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end
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else if (cyc == 4) begin
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if (cmp != 1) $stop;
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end
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else if (cyc == 5) begin
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if (cmp != 0) $stop;
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end
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else if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module adc_netlist(clk, in, gain, cmp);
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input clk;
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input real in;
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input gain;
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output cmp;
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wire pga_out; //TODO: convert to real or support real
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pga_model pga0(.in, .gain, .out(pga_out));
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comparator_model cmp0(.clk, .in(pga_out), .cmp);
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endmodule
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module pga_model(in, gain, out);
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input real in;
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input gain;
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output real out;
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always_comb begin
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out = in * 3.0;
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end
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endmodule
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module comparator_model(clk, in, cmp);
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input clk;
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input real in;
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output logic cmp;
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always_ff @(posedge clk) begin
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cmp <= in > 0.0;
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end
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endmodule
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