verilator/test_regress/t/t_func_crc.pl
Yutetsu TAKATSUKASA bb5384bc50
Optimize bit op tree #2186, #2632, and #2633 (#2751)
* Tests:Add some more signals to t_const_opt_red.v

* Optimize bit op trees such as ~a[2] & a[1] & ~a[0] to 3'b010 == (3'111 & a)

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Apply clang-format

* Don't edit and-or tree.

* Call matchBitOpTree() after V3Expand does its job.

* Internals: Rename newNodep -> newp. No functional change is intended.

* Internals: Remove m_sels. No functional change is intended.

* Internals: Remove stringstream. No functional change is intended.

* Internals: Use V3Number::bitIs1(). No functional change is intended.

* Internals: Use V3Number instead of std::map. Resolved laek. Result should be same.

* Internals: Resolve overload of setPolarity. No functional change is intended.

* Internals: Pass failure reason. No functional change is intended.

* Internals: Add VNUser::toPtr(). No functional change is intended.

* Internals: Use user4 instead of std::map. No functional change is intended.

* Catch up with the AST style aftre V3Expand

* Internals: Rename Context to VarInfo. No functional change is intended.

* Add some more test case

* tests:Add stats to tests
Update stats in t_merge_cond.pl as matchBitopTree does some of them.

* insert CCast if necessary

* small optimization to remove redundant bit mask

* No quick exit even when unoptimizable node is found.

* Simplify removing redundant And

* simplify

* Revert "Internals: Add VNUser::toPtr(). No functional change is intended."

This reverts commit f98dce10db.

* Consider AstWordSel and cleanup

* Update test

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Update src/V3Const.cpp

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>

* Apply clang-format

* Internals: rename variables. No functional change is intended.

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
Co-authored-by: github action <action@example.com>
2021-02-21 18:11:33 +09:00

27 lines
767 B
Perl
Executable File

#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
verilator_flags2 => ["--compiler msvc", "--stats"], # We have deep expressions we want to test
);
execute(
check_finished => 1,
);
if ($Self->{vlt}) {
file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 3888);
}
ok(1);
1;