forked from github/verilator
43 lines
878 B
Systemverilog
43 lines
878 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Rafal Kapuscik
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// SPDX-License-Identifier: CC0-1.0
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//
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class Cls;
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bit [3:0] addr;
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function void set(bit [3:0] addr);
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begin : body
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this.addr = addr;
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end : body
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endfunction
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extern function void setext(bit [3:0] addr);
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endclass
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function void Cls::setext(bit [3:0] addr);
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this.addr = addr;
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endfunction
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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Cls bar;
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Cls baz;
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initial begin
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bar = new();
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baz = new();
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bar.set(4);
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`ifdef TEST_VERBOSE
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$display(bar.addr);
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$display(baz.addr);
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`endif
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if (bar.addr != 4) $stop;
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bar.setext(2);
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if (bar.addr != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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