forked from github/verilator
33 lines
948 B
Systemverilog
33 lines
948 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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logic [31:0] array_assign [3:0];
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logic [31:0] larray_assign [0:3];
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logic [31:0] array_assign2 [6:3];
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logic [31:0] larray_assign2 [3:6];
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initial begin
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array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
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larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
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array_assign2[4:6] = '{32'd4, 32'd3, 32'd2};
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larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2};
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array_assign[4:3] = '{32'd4, 32'd3};
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array_assign[1:-1] = '{32'd4, 32'd3};
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array_assign[1:1] = '{32'd4}; // Ok
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larray_assign[1:1] = '{32'd4}; // Ok
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array_assign2[4:4] = '{32'd4}; // Ok
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larray_assign2[4:4] = '{32'd4}; // Ok
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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