forked from github/verilator
58 lines
1.2 KiB
Systemverilog
58 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int header;
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rand int length;
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extern constraint ex;
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constraint a { header > 0 && header < 1000; }
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constraint b {
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if (64 > header) {
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header < (64'h1 << length);
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}
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}
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constraint b {
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header >= length - 10;
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header <= length;
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}
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constraint c {
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foreach (in_use[i]) {
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!(start_offset <= in_use[i].Xend_offsetX &&
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start_offset + len - 1 >= in_use[i].Xstart_offsetX);
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}
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}
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constraint order { solve length before header; }
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constraint dis {
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disable soft x;
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x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400};
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}
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endclass
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module t (/*AUTOARG*/);
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Packet p;
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initial begin
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int v;
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v = p.randomize();
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if (v != 1) $stop;
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v = p.randomize(1);
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if (v != 1) $stop;
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v = p.randomize(1, 2);
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if (v != 1) $stop;
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v = p.randomize() with {};
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if (v != 1) $stop;
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// Not testing other randomize forms as unused in UVM
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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