forked from github/verilator
87 lines
2.0 KiB
Systemverilog
87 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Methods defined by IEEE:
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// class mailbox #(type T = dynamic_singular_type) ;
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// function new(int bound = 0);
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// function int num();
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// task put( T message);
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// function int try_put( T message);
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// task get( ref T message );
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// function int try_get( ref T message );
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// task peek( ref T message );
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// function int try_peek( ref T message );
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// endclass
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module t(/*AUTOARG*/);
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mailbox m;
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int msg;
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int out;
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initial begin
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m = new(4);
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if (m.num() != 0) $stop;
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if (m.try_get(msg) > 0) $stop;
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msg = 123;
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m.put(msg);
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msg = 0;
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if (m.num() != 1) $stop;
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if (m.try_peek(out) <= 0) $stop;
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if (out != 123) $stop;
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if (m.num() != 0) $stop;
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out = 0;
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if (m.try_peek(out) <= 0) $stop;
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if (out != 123) $stop;
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out = 0;
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if (m.try_get(out) <= 0) $stop;
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if (out != 123) $stop;
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if (m.num() != 0) $stop;
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msg = 124;
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m.put(msg);
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out = 0;
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m.get(out);
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if (out != 124) $stop;
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msg = 125;
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m.put(msg);
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m.put(msg);
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m.try_put(msg);
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m.try_put(msg);
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if (m.num() != 4) $stop;
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if (m.try_put(msg) != 0) $stop;
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if (m.num() != 4) $stop;
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m.get(out);
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m.get(out);
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m.get(out);
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m.get(out);
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if (m.num() != 0) $stop;
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fork
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begin
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#10; // So later then get() starts below
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msg = 130;
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m.put(msg);
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msg = 131;
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m.put(msg);
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end
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begin
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if (m.try_get(msg) != 0) $stop;
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out = 0;
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m.get(out); // Blocks until put
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if (out != 130) $stop;
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out = 0;
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m.get(out);
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if (out != 131) $stop;
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end
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join
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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