forked from github/verilator
33 lines
652 B
Verilog
33 lines
652 B
Verilog
// DESCRIPTION: Verilator: Simple static elaboration case
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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module t (/*AUTOARG*/);
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typedef struct packed {
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logic [ 31 : 0 ] _five;
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} five_t;
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function five_t gimme_five ();
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automatic five_t result;
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result._five = 5;
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return result;
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endfunction
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localparam five_t FIVE = gimme_five();
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initial begin
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if (FIVE._five != 5) begin
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$display("%%Error: Got 0b%b instead of 5", FIVE._five);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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