forked from github/verilator
10 lines
291 B
Systemverilog
10 lines
291 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer t; //<--- Warning ('t' hidden by module 't')
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endmodule
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