forked from github/verilator
32 lines
722 B
Systemverilog
32 lines
722 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Try inline config
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`ifdef verilator
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`verilator_config
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lint_off -rule CASEX -file "t/t_vlt_warn.v"
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`verilog
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`endif
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module t;
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reg width_warn_var_line18 = 2'b11; // Width warning - must be line 18
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reg width_warn2_var_line19 = 2'b11; // Width warning - must be line 19
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reg width_warn3_var_line20 = 2'b11; // Width warning - must be line 20
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initial begin
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casex (1'b1)
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1'b0: $stop;
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endcase
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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