forked from github/verilator
133 lines
3.2 KiB
Systemverilog
133 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef USE_INLINE
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`define INLINE_MODULE /*verilator inline_module*/
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`else
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`define INLINE_MODULE /*verilator public_module*/
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`endif
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module t (/*AUTOARG*/);
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`define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core
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`define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core
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`define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core
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`define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core
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initial begin
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`DRAM1(0)[3] = 130;
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`DRAM1(1)[3] = 131;
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`DRAM2(0)[3] = 230;
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`DRAM2(1)[3] = 231;
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`DRAM3(0)[3] = 330;
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`DRAM3(1)[3] = 331;
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`DRAM4(0)[3] = 430;
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`DRAM4(1)[3] = 431;
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if (`DRAM1(0)[3] !== 130) $stop;
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if (`DRAM1(1)[3] !== 131) $stop;
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if (`DRAM2(0)[3] !== 230) $stop;
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if (`DRAM2(1)[3] !== 231) $stop;
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if (`DRAM3(0)[3] !== 330) $stop;
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if (`DRAM3(1)[3] !== 331) $stop;
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if (`DRAM4(0)[3] !== 430) $stop;
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if (`DRAM4(1)[3] !== 431) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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eh2_lsu_dccm_mem mem (/*AUTOINST*/);
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endmodule
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module eh2_lsu_dccm_mem
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#(
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DCCM_INDEX_DEPTH = 8192,
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DCCM_NUM_BANKS = 2
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)(
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);
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`INLINE_MODULE
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// 8 Banks, 16KB each (2048 x 72)
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for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
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if (DCCM_INDEX_DEPTH == 16384) begin : dccm
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eh2_ram
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#(.depth(16384), .width(32))
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dccm_bank (.*);
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end
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else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
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eh2_ram
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#(.depth(8192), .width(32))
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dccm_bank (.*);
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end
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else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
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eh2_ram
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#(.depth(4096), .width(32))
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dccm_bank (.*);
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end
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end : mem_bank
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// Check that generate doesn't also add a genblk
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generate
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for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank2
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if (DCCM_INDEX_DEPTH == 8192) begin : dccm
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eh2_ram
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#(.depth(8192), .width(32))
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dccm_bank (.*);
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end
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end
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endgenerate
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// Nor this
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generate
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begin
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for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank3
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if (DCCM_INDEX_DEPTH == 8192) begin : dccm
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eh2_ram
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#(.depth(8192), .width(32))
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dccm_bank (.*);
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end
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end
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end
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endgenerate
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// This does
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generate
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begin : sub4
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for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank4
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if (DCCM_INDEX_DEPTH == 8192) begin : dccm
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eh2_ram
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#(.depth(8192), .width(32))
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dccm_bank (.*);
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end
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end
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end
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endgenerate
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// This is an error (previously declared)
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//generate
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// begin
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// eh2_ram
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// #(.depth(8192), .width(32))
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// dccm_bank (.*);
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// end
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// begin
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// eh2_ram
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// #(.depth(8192), .width(32))
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// dccm_bank (.*);
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// end
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//endgenerate
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endmodule
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module eh2_ram #(depth=4096, width=39)
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();
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`INLINE_MODULE
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reg [(width-1):0] ram_core [(depth-1):0];
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endmodule
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