verilator/test_regress/t/t_interface1_modport_trace.out
2019-11-08 08:26:48 -05:00

184 lines
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$version Generated by VerilatedVcd $end
$date Thu Nov 7 18:07:03 2019
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 & clk $end
$scope module t $end
$var wire 1 & clk $end
$var wire 32 # cyc [31:0] $end
$scope module c1 $end
$var wire 32 # i_value [31:0] $end
$scope module isub $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$scope module c2 $end
$var wire 32 # i_value [31:0] $end
$scope module c3 $end
$var wire 32 # i_value [31:0] $end
$scope module isub $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$scope module isub2 $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$scope module itop $end
$var wire 32 $ hidden_from_isub [31:0] $end
$var wire 32 % value [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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