forked from github/verilator
71 lines
1.2 KiB
Systemverilog
71 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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// Very simple test for interface pathclearing
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interface ifc;
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integer hidden_from_isub;
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integer value;
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modport out_modport (output value);
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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ifc itop();
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sub c1 (.isub(itop),
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.i_value(cyc));
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sub2 c2 (.isub2(itop),
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.i_value(cyc));
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always @(*) itop.hidden_from_isub = cyc + 1;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==20) begin
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if (itop.value != 20) $stop;
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if (itop.hidden_from_isub != 21) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub2
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(
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ifc.out_modport isub2,
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input integer i_value
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);
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sub c3 (.isub(isub2),
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.i_value(i_value));
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endmodule
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module sub
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`ifdef NANSI // bug868
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(
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isub, i_value
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);
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ifc.out_modport isub; // Note parenthesis are not legal here
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input integer i_value;
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`else
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(
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ifc.out_modport isub,
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input integer i_value
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);
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`endif
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always @* begin
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isub.value = i_value;
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end
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endmodule
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