forked from github/verilator
37 lines
867 B
Systemverilog
37 lines
867 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Andrew Bardsley.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cnt;
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// This won't compile with tracing as an incorrect declaration is made for
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// the temp variables used to represent the elements of localparam v
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typedef struct packed {
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logic [2:0][31:0] a;
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} t;
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localparam t v[2:0] = '{
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'{'{32'h10000002, 32'h10000001, 32'h10000000}},
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'{'{32'h20000002, 32'h20000001, 32'h20000000}},
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'{'{32'h30000002, 32'h30000001, 32'h30000000}}
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};
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initial cnt = 0;
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always@(posedge clk) begin
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if (cnt < 3) begin
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cnt = cnt + 1;
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end
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else begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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