forked from github/verilator
27 lines
826 B
Systemverilog
27 lines
826 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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`define STRINGIFY(x) `"x`"
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module t;
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reg [5:0] assoc_c[int];
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reg [95:0] assoc_w[int];
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initial begin
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assoc_c[300] = 10; // See if clearing must happen first
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$readmemb("t/t_sys_readmem_b.mem", assoc_c);
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$display("assoc_c=%p", assoc_c);
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$writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_c_b.mem"}, assoc_c);
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$readmemb("t/t_sys_readmem_b.mem", assoc_w);
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// Not conditional with TEST_VERBOSE as found bug with wide display
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$display("assoc_w=%p", assoc_w);
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$writememh({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_writemem_w_h.mem"}, assoc_w);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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