forked from github/verilator
39 lines
899 B
Systemverilog
39 lines
899 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (/*AUTOARG*/);
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int q[$ : 2]; // Shall not go higher than [2], i.e. size 3
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initial begin
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q.push_front(3);
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if (q.size() != 1) $stop;
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q.push_front(2);
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if (q.size() != 2) $stop;
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q.push_front(1);
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if (q.size() != 3) $stop;
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q.push_front(0);
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if (q.size() != 3) $stop;
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if (q[0] != 0) $stop;
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if (q[1] != 1) $stop;
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if (q[2] != 2) $stop;
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q.delete();
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q.push_back(0);
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q.push_back(1);
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q.push_back(2);
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if (q.size() != 3) $stop;
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q.push_back(3);
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if (q.size() != 3) $stop;
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if (q[0] != 0) $stop;
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if (q[1] != 1) $stop;
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if (q[2] != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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