forked from github/verilator
33 lines
479 B
Systemverilog
33 lines
479 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Driss Hafdi
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interface Foo();
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logic quux;
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endinterface
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module Bar();
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always_comb foo.quux = '0;
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endmodule
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module Baz();
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Foo foo();
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Bar bar();
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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Baz baz();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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