forked from github/verilator
60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2011 by Wilson Snyder.
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module t;
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// verilator lint_off PINMISSING
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`ifdef T_GEN_MISSING_BAD
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foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module
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`elsif T_GEN_MISSING
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foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0
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`else
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`error "Bad Test"
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`endif
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endmodule
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module foobar
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#( parameter
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FOO_START = 0,
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FOO_NUM = 2,
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FOO_TYPE = 1
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)
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(
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input wire[FOO_NUM-1:0] foo,
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output wire[FOO_NUM-1:0] bar);
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generate
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begin: g
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genvar j;
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for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1)
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begin: foo_inst;
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if (FOO_TYPE == 0)
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begin: foo_0
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// instatiate foo0
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foo0 i_foo(.x(foo[j]), .y(bar[j]));
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end
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if (FOO_TYPE == 1)
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begin: foo_1
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// instatiate foo1
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foo_not_needed i_foo(.x(foo[j]), .y(bar[j]));
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end
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end
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end
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endgenerate
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endmodule
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module foo0(input wire x, output wire y);
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assign y = ~x;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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