forked from github/verilator
24 lines
404 B
Systemverilog
24 lines
404 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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task tsk(output tfo);
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tfo = 1'b0;
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endtask
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module t (/*AUTOARG*/
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// Outputs
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to
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);
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output reg to[2:0];
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integer i = 0;
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initial begin
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tsk(to[i]);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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