forked from github/verilator
7 lines
176 B
Systemverilog
7 lines
176 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2019 by Wilson Snyder.
|
|
|
|
enum {u=u} e_t;
|