forked from github/verilator
39 lines
969 B
Systemverilog
39 lines
969 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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string mystr;
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reg [2:0] cyc; initial cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) if (mystr != "case-1") $stop;
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if (cyc == 4) if (mystr != "case-4") $stop;
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if (cyc == 6) if (mystr != "bad-default") $stop;
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if (cyc == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @ (cyc) begin
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// verilator lint_off CASEINCOMPLETE
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case (cyc)
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3'b000: mystr = "case-0";
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3'b001: mystr = "case-1";
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3'b010: mystr = "case-2";
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3'b100: mystr = "case-4";
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3'b101: mystr = "case-5";
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default: mystr = "bad-default";
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endcase
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//$display("with_case: %d = %s", cyc, mystr);
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end
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endmodule
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