forked from github/verilator
28 lines
694 B
Systemverilog
28 lines
694 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Jonathon Donaldson.
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module t_bitsel_enum
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(
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output out0,
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output out1
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);
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localparam [6:0] CNST_VAL = 7'h22;
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enum logic [6:0] {
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ENUM_VAL = 7'h33
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} MyEnum;
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assign out0 = CNST_VAL[0];
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// Not supported by NC-verilog nor VCS, but other simulators do
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assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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