forked from github/verilator
4 lines
170 B
Plaintext
4 lines
170 B
Plaintext
[40] %Error: t_assert_synth.v:49: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
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%Error: t/t_assert_synth.v:49: Verilog $stop
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Aborting...
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