forked from github/verilator
706 lines
9.0 KiB
Plaintext
706 lines
9.0 KiB
Plaintext
`line 1 "t/t_preproc.v" 1
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`line 7 "t/t_preproc.v" 0
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`line 7 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc2.vh" 1
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`line 3 "t/t_preproc_inc2.vh" 0
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`line 4 "t/t_preproc_inc2.vh" 0
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At file "t/t_preproc_inc2.vh" line 4
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`line 6 "t/t_preproc_inc2.vh" 0
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`line 1 "t/t_preproc_inc3.vh" 1
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`line 2 "inc3_a_filename_from_line_directive" 0
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`line 6 "inc3_a_filename_from_line_directive" 0
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At file "inc3_a_filename_from_line_directive" line 10
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`line 12 "inc3_a_filename_from_line_directive" 0
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`line 15 "inc3_a_filename_from_line_directive" 0
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`line 19 "inc3_a_filename_from_line_directive" 2
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`line 6 "t/t_preproc_inc2.vh" 0
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`line 8 "t/t_preproc_inc2.vh" 2
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`line 7 "t/t_preproc.v" 0
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`line 12 "t/t_preproc.v" 0
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/*verilator pass_thru comment*/
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`line 14 "t/t_preproc.v" 0
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/*verilator pass_thru_comment2*/
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`line 19 "t/t_preproc.v" 0
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`line 22 "t/t_preproc.v" 0
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wire [3:0] q = {
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1'b1 ,
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1'b0 ,
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1'b1 ,
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1'b1
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};
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`line 29 "t/t_preproc.v" 0
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text.
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`line 31 "t/t_preproc.v" 0
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foo bar
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foobar2
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`line 36 "t/t_preproc.v" 0
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`line 40 "t/t_preproc.v" 0
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`line 46 "t/t_preproc.v" 0
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first part
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`line 46 "t/t_preproc.v" 0
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second part
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`line 46 "t/t_preproc.v" 0
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third part
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{
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`line 47 "t/t_preproc.v" 0
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a,
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`line 47 "t/t_preproc.v" 0
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b,
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`line 47 "t/t_preproc.v" 0
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c}
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Line_Preproc_Check 48
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`line 52 "t/t_preproc.v" 0
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`line 54 "t/t_preproc.v" 0
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deep deep
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`line 58 "t/t_preproc.v" 0
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"Inside: `nosubst"
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"`nosubst"
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`line 63 "t/t_preproc.v" 0
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x y LLZZ x y
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p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s
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`line 69 "t/t_preproc.v" 0
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firstline comma","line LLZZ firstline comma","line
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`line 71 "t/t_preproc.v" 0
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x y LLZZ "a" y
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`line 74 "t/t_preproc.v" 0
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(a,b)(a,b)
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`line 77 "t/t_preproc.v" 0
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$display("left side: \"right side\"")
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`line 80 "t/t_preproc.v" 0
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bar_suffix more
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`line 83 "t/t_preproc.v" 0
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`line 85 "t/t_preproc.v" 0
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$c("Zap(\"",bug1,"\");");;
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`line 86 "t/t_preproc.v" 0
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$c("Zap(\"","bug2","\");");;
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`line 94 "t/t_preproc.v" 0
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initial begin
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$display("pre thrupre thrumid thrupost post: \"right side\"");
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$display("left side: \"right side\"");
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$display("left side: \"right side\"");
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$display("left_side: \"right_side\"");
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$display("na: \"right_side\"");
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$display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
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$display("na: \"nana\"");
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$display("left_side right_side: \"left_side right_side\"");
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$display(": \"\"");
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$display("left side: \"right side\"");
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$display("left side: \"right side\"");
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$display("standalone");
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`line 115 "t/t_preproc.v" 0
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$display("twoline: \"first second\"");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`line 128 "t/t_preproc.v" 0
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`line 133 "t/t_preproc.v" 0
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module add1 ( input wire d1, output wire o1);
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`line 134 "t/t_preproc.v" 0
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wire tmp_d1 = d1;
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`line 134 "t/t_preproc.v" 0
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wire tmp_o1 = tmp_d1 + 1;
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`line 134 "t/t_preproc.v" 0
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assign o1 = tmp_o1 ;
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endmodule
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module add2 ( input wire d2, output wire o2);
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`line 137 "t/t_preproc.v" 0
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wire tmp_d2 = d2;
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`line 137 "t/t_preproc.v" 0
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wire tmp_o2 = tmp_d2 + 1;
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`line 137 "t/t_preproc.v" 0
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assign o2 = tmp_o2 ;
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endmodule
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`line 140 "t/t_preproc.v" 0
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`line 147 "t/t_preproc.v" 0
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`line 151 "t/t_preproc.v" 0
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`line 151 "t/t_preproc.v" 0
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generate for (i=0; i<(3); i=i+1) begin
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`line 151 "t/t_preproc.v" 0
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psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";
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`line 151 "t/t_preproc.v" 0
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psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";
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`line 151 "t/t_preproc.v" 0
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end endgenerate
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`line 155 "t/t_preproc.v" 0
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module prot();
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`protected
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I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
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#nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
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`endprotected
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`line 160 "t/t_preproc.v" 0
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endmodule
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`line 165 "t/t_preproc.v" 0
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`line 173 "t/t_preproc.v" 0
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begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
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begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
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begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
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`line 179 "t/t_preproc.v" 0
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`line 180 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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`line 3 "t/t_preproc_inc4.vh" 0
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`line 5 "t/t_preproc_inc4.vh" 0
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`line 7 "t/t_preproc_inc4.vh" 2
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`line 180 "t/t_preproc.v" 0
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`line 181 "t/t_preproc.v" 0
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`line 184 "t/t_preproc.v" 0
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`line 186 "t/t_preproc.v" 0
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`line 193 "t/t_preproc.v" 0
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$blah("ab,cd","e,f");
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$blah(this.logfile,vec);
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$blah(this.logfile,vec[1,2,3]);
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$blah(this.logfile,{blah.name(), " is not foo"});
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`line 202 "t/t_preproc.v" 0
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`pragma foo = 1
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`default_nettype none
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`default_nettype uwire
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`line 209 "t/t_preproc.v" 0
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`line 213 "t/t_preproc.v" 0
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Line_Preproc_Check 213
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`line 218 "t/t_preproc.v" 0
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(p,q)
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`line 225 "t/t_preproc.v" 0
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(x,y)
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Line_Preproc_Check 226
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`line 231 "t/t_preproc.v" 0
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beginend
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beginend
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"beginend"
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`line 241 "t/t_preproc.v" 0
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`\esc`def
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`line 245 "t/t_preproc.v" 0
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Not a \`define
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`line 249 "t/t_preproc.v" 0
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x,y)--bee submacro has comma paren
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`line 257 "t/t_preproc.v" 0
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$display("bits %d %d", $bits(foo), `10);
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`line 262 "t/t_preproc.v" 0
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`line 265 "t/t_preproc.v" 0
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`line 270 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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`line 282 "t/t_preproc.v" 0
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assign a3 = ~b3 ;
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`line 282 "t/t_preproc.v" 0
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`line 284 "t/t_preproc.v" 0
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\
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`line 293 "t/t_preproc.v" 0
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`line 293 "t/t_preproc.v" 0
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`line 293 "t/t_preproc.v" 0
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`line 293 "t/t_preproc.v" 0
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def i
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`line 297 "t/t_preproc.v" 0
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`line 301 "t/t_preproc.v" 0
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`line 307 "t/t_preproc.v" 0
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1 /*verilator NOT IN DEFINE*/ (nodef)
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2 /*verilator PART OF DEFINE*/ (hasdef)
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3
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`line 309 "t/t_preproc.v" 0
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/*verilator NOT PART
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OF DEFINE*/ (nodef)
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`line 310 "t/t_preproc.v" 0
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4
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`line 310 "t/t_preproc.v" 0
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/*verilator PART
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OF DEFINE*/ (nodef)
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`line 311 "t/t_preproc.v" 0
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5 also in
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`line 311 "t/t_preproc.v" 0
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also3 (nodef)
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HAS a NEW
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`line 314 "t/t_preproc.v" 0
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LINE
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`line 318 "t/t_preproc.v" 0
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`line 331 "t/t_preproc.v" 0
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`line 334 "t/t_preproc.v" 0
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EXP: clxx_scen
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clxx_scen
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EXP: clxx_scen
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"clxx_scen"
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EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
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`line 340 "t/t_preproc.v" 0
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do
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`line 340 "t/t_preproc.v" 0
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`line 340 "t/t_preproc.v" 0
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`line 340 "t/t_preproc.v" 0
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`line 340 "t/t_preproc.v" 0
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`line 340 "t/t_preproc.v" 0
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if (start("t/t_preproc.v", 340)) begin
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`line 340 "t/t_preproc.v" 0
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`line 340 "t/t_preproc.v" 0
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message({"Blah-", "clx_scen", " end"});
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`line 340 "t/t_preproc.v" 0
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end
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`line 340 "t/t_preproc.v" 0
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`line 340 "t/t_preproc.v" 0
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while(0);
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`line 344 "t/t_preproc.v" 0
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`line 348 "t/t_preproc.v" 0
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`line 349 "t/t_preproc.v" 0
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`line 351 "t/t_preproc.v" 0
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EXP: This is fooed
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This is fooed
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EXP: This is fooed_2
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This is fooed_2
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`line 357 "t/t_preproc.v" 0
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np
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np
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`line 362 "t/t_preproc.v" 0
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`line 378 "t/t_preproc.v" 0
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`line 382 "t/t_preproc.v" 0
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hello3hello3hello3
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hello4hello4hello4hello4
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`line 386 "t/t_preproc.v" 0
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`line 388 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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`line 3 "t/t_preproc_inc4.vh" 0
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`line 5 "t/t_preproc_inc4.vh" 0
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`line 7 "t/t_preproc_inc4.vh" 2
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`line 389 "t/t_preproc.v" 0
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`line 393 "t/t_preproc.v" 0
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`line 397 "t/t_preproc.v" 0
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Line_Preproc_Check 401
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`line 404 "t/t_preproc.v" 0
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Line_Preproc_Check 407
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"FOO \
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BAR " "arg_line1 \
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arg_line2" "FOO \
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BAR "
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`line 410 "t/t_preproc.v" 0
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Line_Preproc_Check 410
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`line 414 "t/t_preproc.v" 0
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`line 418 "t/t_preproc.v" 0
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abc
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`line 424 "t/t_preproc.v" 0
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EXP: sonet_frame
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sonet_frame
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`line 430 "t/t_preproc.v" 0
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EXP: sonet_frame
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sonet_frame
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`line 435 "t/t_preproc.v" 0
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EXP: sonet_frame
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sonet_frame
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`line 441 "t/t_preproc.v" 0
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EXP: module zzz ; endmodule
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module zzz ; endmodule
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module zzz ; endmodule
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`line 447 "t/t_preproc.v" 0
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EXP: module a_b ; endmodule
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module a_b ; endmodule
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module a_b ; endmodule
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`line 454 "t/t_preproc.v" 2
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