forked from github/verilator
17 lines
499 B
Systemverilog
17 lines
499 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// Arguable, but we won't throw a hidden warning on tcp_port
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parameter tcp_port = 5678;
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import "DPI-C" function int dpii_func ( input integer tcp_port,
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output longint obj );
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// 't' is hidden:
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integer t;
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endmodule
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