forked from github/verilator
19 lines
409 B
Systemverilog
19 lines
409 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(
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input wire clk
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);
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integer cyc; initial cyc = 0;
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integer unchanged; initial unchanged = 42;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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end
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endmodule
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