forked from github/verilator
22 lines
448 B
Systemverilog
22 lines
448 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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// verilator lint_off IGNOREDRETURN
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func(0, 1'b1);
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end
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function automatic int func
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(
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input int a,
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output bit b );
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return 0;
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endfunction
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endmodule
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