forked from github/verilator
ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
40 lines
1.3 KiB
Verilog
40 lines
1.3 KiB
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg [40:0] quad; initial quad = 41'ha_bbbb_cccc;
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reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678;
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reg [31:0] str; initial str = "\000\277\021\n";
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reg [47:0] str2; initial str2 = "\000what!";
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reg [79:0] str3; initial str3 = "\000hmmm!1234";
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initial begin
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$write("[%0t] ", $time);
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$write("%m: Hi\n");
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// Display formatting
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$display("[%0t] %%X=%X %%D=%D %%0X=%0X %%0O=%0O %%B=%B", $time,
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quad[5:0], quad[5:0], quad[5:0], quad[5:0], quad[5:0]);
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$display("[%0t] %%x=%x %%d=%d %%0x=%0x %%0o=%0o %%b=%b", $time,
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quad[5:0], quad[5:0], quad[5:0], quad[5:0], quad[5:0]);
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$display("[%0t] %%x=%x %%0x=%0x %%o=%o %%b=%b", $time,
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quad, quad, quad, quad);
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$display("[%0t] %%x=%x %%0x=%0x %%o=%o %%b=%b", $time,
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wide, wide, wide, wide);
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$display;
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// Not testing %0s, it does different things in different simulators
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$display("[%0t] %%s=%s %%s=%s %%s=%s", $time,
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str2[7:0], str2, str3);
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// Str check
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`ifndef nc // NC-Verilog 5.3 chokes on this test
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if (str !== 32'h00_bf_11_0a) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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