forked from github/verilator
157 lines
2.2 KiB
Plaintext
157 lines
2.2 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$date Thu Mar 13 20:06:49 2014
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$end
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$timescale 1ns $end
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$scope module top $end
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$var wire 1 0 clk $end
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$scope module v $end
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$var wire 1 0 clk $end
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$var wire 32 # cyc [31:0] $end
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$var wire 2 ' v_arrp [2:1] $end
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$var wire 2 ( v_arrp_arrp [2:1] $end
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$var wire 2 ) v_arrp_strp [1:0] $end
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$var wire 1 1 v_arru(1) $end
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$var wire 1 2 v_arru(2) $end
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$var wire 2 * v_arru_arrp(3) [2:1] $end
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$var wire 2 + v_arru_arrp(4) [2:1] $end
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$var wire 1 3 v_arru_arru(3)(1) $end
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$var wire 1 4 v_arru_arru(3)(2) $end
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$var wire 1 5 v_arru_arru(4)(1) $end
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$var wire 1 6 v_arru_arru(4)(2) $end
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$var wire 2 , v_arru_strp(3) [1:0] $end
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$var wire 2 - v_arru_strp(4) [1:0] $end
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$var wire 2 $ v_strp [1:0] $end
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$var wire 4 % v_strp_strp [3:0] $end
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$var wire 2 & v_unip_strp [1:0] $end
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$scope module p2 $end
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$var wire 32 7 PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 8 PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 . b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 / a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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b00000000000000000000000000000010 7
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10
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