forked from github/verilator
17 lines
495 B
Verilog
17 lines
495 B
Verilog
// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Lane Brooks
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module top (input A, input B, input SEL, output Y1, output Y2, output Z);
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io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1));
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pass io2(.A(B), .OE(!SEL), .Z(Z), .Y(Y2));
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endmodule
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module pass (input A, input OE, inout Z, output Y);
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io io(.A(A), .OE(OE), .Z(Z), .Y(Y));
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endmodule
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module io (input A, input OE, inout Z, output Y);
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assign Z = (OE) ? A : 1'bz;
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assign Y = Z;
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endmodule
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