forked from github/verilator
20 lines
540 B
Systemverilog
20 lines
540 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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wire (weak0, highz1) a = 1;
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wire (strong1, highz0) b = 0;
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wire (highz0, pull1) c = 0;
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wire (highz1, supply0) d = 1;
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always begin
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if (a === 1'bz && b === 1'bz && c === 1'bz && d === 1'bz) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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