forked from github/verilator
35 lines
584 B
Systemverilog
35 lines
584 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2016 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(
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input wire clk,
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input wire a,
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input wire b
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);
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integer q;
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// bug1120
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always @ (a or posedge clk)
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begin
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if (a)
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q = 0;
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else
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q = q + 1;
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end
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// bug934
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integer qb;
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always @((a && b) or posedge clk) begin
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if (a)
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qb = 0;
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else
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qb = qb + 1;
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end
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endmodule
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