forked from github/verilator
26 lines
459 B
Systemverilog
26 lines
459 B
Systemverilog
module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg clk_en = 1'b0;
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wire clk_gated = clk & clk_en;
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wire [1:0] clks = {1'b0, clk_gated};
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always @(posedge clks[0]) begin
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$display("ERROR: clks[0] should not be active!");
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$stop;
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end
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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