forked from github/verilator
101 lines
2.6 KiB
Verilog
101 lines
2.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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wire monclk = ~clk;
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int in;
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int fr_a;
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int fr_b;
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int fr_chk;
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sub sub (.*);
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
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`endif
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cyc <= cyc + 1;
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in <= {in[30:0], in[31]^in[2]^in[0]};
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if (cyc==0) begin
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// Setup
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in <= 32'hd70a4497;
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end
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else if (cyc<3) begin
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end
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else if (cyc<10) begin
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if (fr_chk != fr_a) $stop;
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if (fr_chk != fr_b) $stop;
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end
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else if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
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import "DPI-C" context function void mon_register_b(string name, int isOut);
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import "DPI-C" context function void mon_register_done();
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module sub (/*AUTOARG*/
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// Outputs
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fr_a, fr_b, fr_chk,
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// Inputs
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in
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);
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`systemc_imp_header
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void mon_class_name(const char* namep);
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void mon_register_a(const char* namep, void* sigp, bool isOut);
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bool mon_eval();
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`verilog
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input int in /*verilator public_flat*/;
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output int fr_a /*verilator public_flat*/;
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output int fr_b /*verilator public_flat*/;
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output int fr_chk;
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reg [3:0] onearray [1:2] /*verilator public_flat*/;
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reg [3:0] twoarray [1:2][3:4] /*verilator public_flat*/;
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always @* fr_chk = in + 1;
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initial begin
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// Test the naming
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$c("mon_class_name(name());");
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mon_scope_name("%m");
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// Scheme A - pass pointer directly
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$c("mon_register_a(\"in\",&",in,",false);");
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$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
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// Scheme B - use VPIish callbacks to see what signals exist
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mon_register_b("in", 0);
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mon_register_b("fr_b", 1);
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mon_register_done();
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end
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always @(posedge t.monclk) begin
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// Hack - Write all outputs, so the data will get scheduled to propagate out of this module
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// FUTURE Long term, we should detect a public signal has been written
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// with a new value, and create an event that flips monclk automatically
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if ($c1("mon_eval()")) begin
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// This code doesn't execute, just is here so verilator schedules the code.
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fr_a = 0;
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fr_b = 0;
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end
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end
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endmodule
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