forked from github/verilator
24 lines
440 B
Verilog
24 lines
440 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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// verilator lint_off SYMRSVDWORD
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module t (/*AUTOARG*/
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// Inputs
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bool
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);
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input bool; // BAD
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reg vector; // OK, as not public
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reg switch /*verilator public*/; // Bad
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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