forked from github/verilator
35 lines
628 B
Systemverilog
35 lines
628 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int val;
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event e;
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always @val $write("val=%0d\n", val);
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initial begin
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val = 1;
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@e val = 2;
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fork begin
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@e #1 val = 3;
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->e;
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end join_none
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->e;
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val = @e val + 2;
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val <= @e val + 2;
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fork begin
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@e val = 5;
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->e;
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end join_none
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->e;
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->e;
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#1 $write("*-* All Finished *-*\n");
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$finish;
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end
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initial #1 ->e;
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endmodule
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