forked from github/verilator
a2ffe86a36
git-svn-id: file://localhost/svn/verilator/trunk/verilator@976 77ca24e4-aefa-0310-84f0-b9a241c72d87
43 lines
802 B
Verilog
43 lines
802 B
Verilog
// $Id$
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// DESCRIPTION: Verilator Test: Top level main for invoking model
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//
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// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// General Public License or the Perl Artistic License.
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module sim_main;
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/*verilator public_module*/
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reg clk;
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reg check;
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wire done;
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vgen vgen (/*AUTOINST*/
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// Outputs
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.done (done),
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// Inputs
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.clk (clk),
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.check (check));
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integer i;
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initial begin
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check = 1'b0;
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clk = 1'b0;
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for (i=0; i<10*vgen.CYCLES; i=i+1) begin
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#5;
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clk = ~clk;
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#5;
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clk = ~clk;
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end
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check = 1'b1;
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for (i=0; i<10; i=i+1) begin
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#5;
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clk = ~clk;
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#5;
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clk = ~clk;
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end
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end
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endmodule
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