forked from github/verilator
222 lines
10 KiB
C++
222 lines
10 KiB
C++
// -*- C++ -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Large 4-state numbers
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//
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// Code available from: http://www.veripool.org/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// General Public License or the Perl Artistic License.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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#ifndef _V3NUMBER_H_
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#define _V3NUMBER_H_ 1
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#include "config_build.h"
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#include "verilatedos.h"
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#include <vector>
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#include "V3Error.h"
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//============================================================================
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class V3Number {
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// Large 4-state number handling
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int m_width; // Width as specified/calculated.
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bool m_sized:1; // True if the user specified the width, else we track it.
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bool m_signed:1; // True if signed value
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bool m_autoExtend:1; // True if SystemVerilog extend-to-any-width
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FileLine* m_fileline;
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vector<uint32_t> m_value; // The Value, with bit 0 being in bit 0 of this vector (unless X/Z)
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vector<uint32_t> m_valueX; // Each bit is true if it's X or Z, 10=z, 11=x
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// METHODS
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void init(FileLine* fileline, int width);
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V3Number& setZero();
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V3Number& setSingleBits(char value);
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void opCleanThis();
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public:
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FileLine* fileline() const { return m_fileline; }
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void fileline(FileLine* fl) { m_fileline=fl; }
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V3Number& setQuad(vluint64_t value);
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V3Number& setLong(uint32_t value);
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void setBit (int bit, char value) { // Note must be pre-zeroed!
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if (bit>=m_width) return;
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if (value=='0'||value==0) m_value [bit/32] &= ~(1UL<<(bit&31));
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else {
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if (value=='1'||value=='x'||value==1||value==3) m_value [bit/32] |= (1UL<<(bit&31));
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if (value=='z'||value=='x'||value==2||value==3) m_valueX[bit/32] |= (1UL<<(bit&31));
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}
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}
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private:
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char bitIs (int bit) const {
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if (bit>=m_width) {
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bit = m_width-1;
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// We never sign extend
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return ( "00zx"[(((m_value[bit/32] & (1UL<<(bit&31)))?1:0)
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| ((m_valueX[bit/32] & (1UL<<(bit&31)))?2:0))] );
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}
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return ( "01zx"[(((m_value[bit/32] & (1UL<<(bit&31)))?1:0)
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| ((m_valueX[bit/32] & (1UL<<(bit&31)))?2:0))] ); }
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char bitIsExtend (int bit) const {
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if (bit>=m_width) {
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bit = m_width-1;
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// We do sign extend
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return ( "01zx"[(((m_value[bit/32] & (1UL<<(bit&31)))?1:0)
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| ((m_valueX[bit/32] & (1UL<<(bit&31)))?2:0))] );
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}
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return ( "01zx"[(((m_value[bit/32] & (1UL<<(bit&31)))?1:0)
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| ((m_valueX[bit/32] & (1UL<<(bit&31)))?2:0))] ); }
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bool bitIs0 (int bit) const {
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if (bit>=m_width) return !bitIsXZ(m_width-1);
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return ( (m_value[bit/32] & (1UL<<(bit&31)))==0 && !(m_valueX[bit/32] & (1UL<<(bit&31))) ); }
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bool bitIs1 (int bit) const {
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if (bit>=m_width) return false;
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return ( (m_value[bit/32] & (1UL<<(bit&31))) && !(m_valueX[bit/32] & (1UL<<(bit&31))) ); }
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bool bitIs1Extend (int bit) const {
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if (bit>=m_width) return bitIs1Extend(m_width-1);
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return ( (m_value[bit/32] & (1UL<<(bit&31))) && !(m_valueX[bit/32] & (1UL<<(bit&31))) ); }
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bool bitIsX (int bit) const {
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if (bit>=m_width) return bitIsZ(m_width-1);
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return ( (m_value[bit/32] & (1UL<<(bit&31))) && (m_valueX[bit/32] & (1UL<<(bit&31))) ); }
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bool bitIsXZ(int bit) const {
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if (bit>=m_width) return bitIsXZ(m_width-1);
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return ( (m_valueX[bit/32] & (1UL<<(bit&31))) );
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}
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bool bitIsZ (int bit) const {
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if (bit>=m_width) return bitIsZ(m_width-1);
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return ( (~m_value[bit/32] & (1UL<<(bit&31))) && (m_valueX[bit/32] & (1UL<<(bit&31))) ); }
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uint32_t bitsValue(int lsb, int nbits) const {
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uint32_t v=0;
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for (int bitn=0; bitn<nbits; bitn++) { v |= (bitIs1(lsb+bitn)<<bitn); }
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return v;
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}
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int words() const { return ((width()+31)/32); }
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public:
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class VerilogString {}; // for creator type-overload selection
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// CONSTRUCTORS
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V3Number(FileLine* fileline) { init(fileline, 1); }
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V3Number(FileLine* fileline, int width) { init(fileline, width); }; // 0=unsized
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V3Number(FileLine* fileline, int width, uint32_t value) { init(fileline, width); m_value[0]=value; }
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V3Number(FileLine* fileline, const char* source); // Create from a verilog 32'hxxxx number.
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V3Number(VerilogString, FileLine* fileline, const string& vvalue);
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// SETTERS
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V3Number& setAllBitsX();
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V3Number& setAllBitsZ();
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V3Number& setMask(int nbits); // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc
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// ACCESSORS
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string ascii(bool prefixed=true, bool cleanVerilog=false) const;
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string displayed(const string& format) const;
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static bool displayedFmtLegal(char format); // Is this a valid format letter?
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int width() const { return m_width; }
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int minWidth() const; // Minimum width that can represent this number (~== log2(num)+1)
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bool sized() const { return m_sized; }
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bool autoExtend() const { return m_autoExtend; }
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bool isSigned() const { return m_signed; } // Only correct for parsing of numbers from strings, otherwise not used (use AstConst::isSigned())
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bool isNegative() const { return bitIs1(width()-1); }
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bool isFourState() const { for (int i=0;i<words();i++) {if (m_valueX[i]) return true;} return false; }
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bool isEqZero() const;
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bool isNeqZero() const;
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bool isEqOne() const;
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bool isEqAllOnes(int optwidth=0) const;
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bool isCaseEq(const V3Number& rhsp) const; // operator==
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void width(int width, bool sized=true);
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void isSigned(bool ssigned) { m_signed=ssigned; }
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bool isUnknown() const;
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uint32_t asInt() const;
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vlsint32_t asSInt() const;
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vluint64_t asQuad() const;
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vlsint64_t asSQuad() const;
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uint32_t asHash() const;
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uint32_t dataWord(int word) const;
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uint32_t countOnes() const;
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uint32_t mostSetBitP1() const; // Highest bit set plus one, IE for 16 return 5, for 0 return 0.
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// STATICS
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static int log2b(uint32_t num);
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typedef V3Number& (*UniopFuncp)(V3Number&);
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typedef V3Number& (*BiopFuncp) (V3Number&, V3Number&);
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// MATH
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// "this" is the output, as we need the output width before some computations
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V3Number& isTrue (const V3Number& lhs);
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V3Number& opBitsNonX(const V3Number& lhs); // 0/1->1, X/Z->0
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V3Number& opBitsOne (const V3Number& lhs); // 1->1, 0/X/Z->0
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V3Number& opBitsXZ (const V3Number& lhs); // 0/1->0, X/Z->1
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//
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V3Number& opAssign (const V3Number& lhs);
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V3Number& opExtendS (const V3Number& lhs); // Sign extension
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V3Number& opRedOr (const V3Number& lhs);
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V3Number& opRedAnd (const V3Number& lhs);
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V3Number& opRedXor (const V3Number& lhs);
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V3Number& opRedXnor (const V3Number& lhs);
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V3Number& opCountOnes(const V3Number& lhs);
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V3Number& opIsUnknown(const V3Number& lhs);
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V3Number& opOneHot (const V3Number& lhs);
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V3Number& opOneHot0 (const V3Number& lhs);
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V3Number& opCLog2 (const V3Number& lhs);
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V3Number& opClean (const V3Number& lhs, uint32_t bits);
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V3Number& opConcat (const V3Number& lhs, const V3Number& rhs);
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V3Number& opRepl (const V3Number& lhs, const V3Number& rhs);
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V3Number& opRepl (const V3Number& lhs, uint32_t rhs);
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V3Number& opRange (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
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V3Number& opRange (const V3Number& lhs, uint32_t rhs, uint32_t ths);
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V3Number& opCond (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
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V3Number& opCaseEq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opCaseNeq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opWildEq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opWildNeq (const V3Number& lhs, const V3Number& rhs);
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// "standard" math
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V3Number& opNot (const V3Number& lhs);
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V3Number& opLogNot (const V3Number& lhs);
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V3Number& opLogAnd (const V3Number& lhs, const V3Number& rhs);
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V3Number& opLogOr (const V3Number& lhs, const V3Number& rhs);
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V3Number& opUnaryMin(const V3Number& lhs);
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V3Number& opAdd (const V3Number& lhs, const V3Number& rhs);
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V3Number& opSub (const V3Number& lhs, const V3Number& rhs);
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V3Number& opMul (const V3Number& lhs, const V3Number& rhs);
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V3Number& opMulS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opDiv (const V3Number& lhs, const V3Number& rhs);
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V3Number& opDivS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opModDiv (const V3Number& lhs, const V3Number& rhs);
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V3Number& opModDivS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opPow (const V3Number& lhs, const V3Number& rhs);
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V3Number& opPowS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opAnd (const V3Number& lhs, const V3Number& rhs);
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V3Number& opChangeXor(const V3Number& lhs, const V3Number& rhs);
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V3Number& opXor (const V3Number& lhs, const V3Number& rhs);
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V3Number& opXnor (const V3Number& lhs, const V3Number& rhs);
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V3Number& opOr (const V3Number& lhs, const V3Number& rhs);
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V3Number& opShiftR (const V3Number& lhs, const V3Number& rhs);
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V3Number& opShiftRS (const V3Number& lhs, const V3Number& rhs); // Arithmetic w/carry
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V3Number& opShiftL (const V3Number& lhs, const V3Number& rhs);
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// Comparisons
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V3Number& opEq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opNeq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opGt (const V3Number& lhs, const V3Number& rhs);
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V3Number& opGtS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opGte (const V3Number& lhs, const V3Number& rhs);
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V3Number& opGteS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opLt (const V3Number& lhs, const V3Number& rhs);
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V3Number& opLtS (const V3Number& lhs, const V3Number& rhs); // Signed
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V3Number& opLte (const V3Number& lhs, const V3Number& rhs);
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V3Number& opLteS (const V3Number& lhs, const V3Number& rhs); // Signed
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};
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inline ostream& operator<<(ostream& os, V3Number rhs) { return os<<rhs.ascii(); }
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#endif // Guard
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