forked from github/verilator
25 lines
948 B
XML
25 lines
948 B
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_xml_output.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_xml_output.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="d6" loc="d,6,8,6,9" name="m" submodname="m" hier="m"/>
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</cells>
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<netlist>
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<module fl="d6" loc="d,6,8,6,9" name="m" origName="m">
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<var fl="d7" loc="d,7,10,7,13" name="clk" tag="foo_op" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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</module>
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<typetable fl="a0" loc="a,0,0,0,0">
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<basicdtype fl="d7" loc="d,7,10,7,13" id="1" name="logic"/>
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</typetable>
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</netlist>
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</verilator_xml>
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